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E2G0010-17-41
Semiconductor MSM514256C/CL
Semiconductor
This version: Jan. 1998 MSM514256C/CL Previous version: May 1997
262,144-Word 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM514256C/CL is a 262,144-word 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514256C/CL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM514256C/CL is available in a 20-pin plastic DIP, 26/20-pin plastic SOJ, or 20-pin plastic ZIP. The MSM514256CL (the low-power version) is specially designed for lower-power applications.
FEATURES
* 262,144-word 4-bit configuration * Single 5 V power supply, 10% tolerance * Input : TTL compatible, low input capacitance * Output : TTL compatible, 3-state * Refresh : 512 cycles/8 ms, 512 cycles/64 ms (L-version) * Fast page mode, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Package options: 20-pin 300 mil plastic DIP (DIP20-P-300-2.54-W1) (Product : MSM514256C/CL-xxRS) 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514256C/CL-xxJS) 20-pin 400 mil plastic ZIP (ZIP20-P-400-1.27) (Product : MSM514256C/CL-xxZS) xx indicates speed rank.
PRODUCT FAMILY
Family MSM514256C/CL-45 MSM514256C/CL-50 MSM514256C/CL-60 MSM514256C/CL-70 Access Time (Max.) tRAC tAA tCAC tOEA 45 ns 24 ns 14 ns 14 ns 50 ns 26 ns 14 ns 14 ns 60 ns 30 ns 15 ns 15 ns 70 ns 35 ns 20 ns 20 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 90 ns 100 ns 120 ns 130 ns 468 mW 446 mW 385 mW 330 mW 5.5 mW/ 1.1 mW (L-version)
1/17
Semiconductor
PIN CONFIGURATION (TOP VIEW)
DQ1 1 DQ2 2 WE 3 RAS 4 NC 5 A0 6 A1 7 A2 8 A3 9 VCC 10 20 VSS
DQ1 1 19 DQ4 18 DQ3 17 CAS 16 OE 15 A8 14 A7 13 A6 12 A5 11 A4 DQ2 2 WE 3 NC 5 A0 9 RAS 4 A1 10 A2 11 A3 12 VCC 13 Pin Name A0 - A8 RAS CAS DQ1 - DQ4 OE WE VCC VSS NC
MSM514256C/CL
26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE 18 A8 17 A7 16 A6 15 A5 14 A4
OE 1 DQ3 3 VSS 5 DQ2 7 RAS 9 A0 11 A2 13 VCC 15 A5 17 A7 19
2 CAS 4 DQ4 6 DQ1 8 WE NO LEAD 12 A1 14 A3 16 A4 18 A6 20 A8
20-Pin Plastic ZIP 26/20-Pin Plastic SOJ
20-Pin Plastic DIP
Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5 V) Ground (0 V) No Connection
2/17
Semiconductor
MSM514256C/CL
BLOCK DIAGRAM
RAS CAS Timing Generator Timing Generator
9
Column Address Buffers Internal Address Counter
9
Column Decoders
Write Clock Generator
WE OE
4
Output Buffers Input Buffers
4 4
A0 - A8
Refresh Control Clock
Sense Amplifiers
4
I/O Selector
4 4 4
DQ1 - DQ4
9
Row Address Buffers
9
Row Decoders
Word Drivers
Memory Cells
VCC On Chip VBB Generator VSS
3/17
Semiconductor
MSM514256C/CL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA W C C
*: Ta = 25C Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -1.0 Typ. 5.0 0 -- -- Max. 5.5 0 6.5 0.8 (Ta = 0C to 70C) Unit V V V V
Capacitance
Parameter Input Capacitance (A0 - A8) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ4) Symbol CIN1 CIN2 CI/O Typ. -- -- --
(VCC = 5 V 10%, Ta = 25C, f = 1 MHz) Max. 5 5 6 Unit pF pF pF
4/17
Semiconductor DC Characteristics
MSM514256C/CL
(VCC = 5 V 10%, Ta = 0C to 70C)
Symbol
Parameter Output High Voltage Output Low Voltage Input Leakage Current
Condition IOH = -5.0 mA IOL = 4.2 mA 0 V VI 6.5 V; All other pins not under test = 0 V DQ disable 0 V VO 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH
MSM514256 MSM514256 MSM514256 MSM514256 C/CL-45 C/CL-50 C/CL-60 C/CL-70 Unit Note
Min. Max. Min. Max. Min. Max. Min. Max. VOH VOL ILI 2.4 0 -10 VCC 0.4 10 2.4 0 -10 VCC 0.4 10 2.4 0 -10 VCC 0.4 10 2.4 0 -10 VCC 0.4 10 V V mA
Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup)
ILO
-10
10
-10
10
-10
10
-10
10
mA
ICC1
-- -- -- -- --
85 2 1 200 85
-- -- -- -- --
80 2 1 200 80
-- -- -- -- --
70 2 1 200 70
-- -- -- -- --
60 2 1 200 60
mA
1, 2
ICC2
RAS, CAS VCC -0.2 V RAS cycling,
mA mA mA
1 1, 5 1, 2
ICC3
CAS = VIH, tRC = Min. RAS = VIH,
ICC5
CAS = VIL, DQ = enable
--
5
--
5
--
5
--
5
mA
1
ICC6
RAS cycling, CAS before RAS RAS = VIL,
--
85
--
80
--
70
--
60
mA
1, 2
ICC7
CAS cycling, tPC = Min. tRC = 125 ms,
--
80
--
75
--
65
--
55
mA
1, 3
ICC10 CAS before RAS, tRAS 1 ms
--
300
--
300
--
300
--
300
mA
1, 2, 4, 5
Notes : 1. 2. 3. 4. 5.
ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC - 0.2 V VIH 6.5 V, -1.0 V VIL 0.2 V. L-version.
5/17
Semiconductor AC Characteristics (1/2)
MSM514256C/CL
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3, 4, 5 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS
Symbol
MSM514256 MSM514256 MSM514256 MSM514256 C/CL-45 C/CL-50 C/CL-60 C/CL-70 Unit Note
Min. Max. Min. Max. Min. Max. Min. Max. tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ 90 140 34 75 -- -- -- -- -- 0 0 0 3 -- -- 35 -- -- -- -- 45 14 24 28 14 -- 10 10 50 8 64 -- 100 150 36 77 -- -- -- -- -- 0 0 0 3 -- -- 40 -- -- -- -- 50 14 26 30 14 -- 10 10 50 8 64 -- 120 170 40 90 -- -- -- -- -- 0 0 0 3 -- -- 50 -- -- -- -- 60 15 30 35 15 -- 10 10 50 8 64 -- 130 185 45 95 -- -- -- -- -- 0 0 0 3 -- -- 50 -- -- -- -- 70 20 35 40 20 -- 10 10 50 8 64 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns 6, 7, 8 6, 7 6, 8 6 6 6 9 9 3
CAS to Data Output Buffer Turn-off Delay Time tOFF OE to Data Output Buffer Turn-off Delay Time tOEZ Transition Time Refresh Period Refresh Period (L-version) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time tT tREF tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL
45 10,000 50 10,000 60 10,000 70 10,000 ns 45 100,000 50 100,000 60 100,000 70 100,000 ns 14 10 10 45 5 28 17 12 0 7 0 12 35 24 -- -- -- -- -- -- 31 21 -- -- -- -- -- -- 14 10 10 50 5 30 18 13 0 8 0 13 40 26 -- -- -- -- -- -- 36 24 -- -- -- -- -- -- 15 10 10 60 5 35 20 15 0 10 0 15 50 30 -- -- -- -- -- -- 45 30 -- -- -- -- -- -- 20 10 10 70 5 40 20 15 0 10 0 15 55 35 -- -- -- -- -- -- 50 35 -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 8
14 10,000 14 10,000 15 10,000 20 10,000 ns
6/17
Semiconductor AC Characteristics (2/2)
MSM514256C/CL
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3, 4, 5 Parameter Read Command Set-up Time Read Command Hold Time Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time
Symbol
MSM514256 MSM514256 MSM514256 MSM514256 C/CL-45 C/CL-50 C/CL-60 C/CL-70 Unit Note
Min. Max. Min. Max. Min. Max. Min. Max. tRCS tRCH tWCS tWCH tWCR tWP tOEH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD 0 0 0 0 10 35 10 12 14 14 0 12 35 12 36 48 70 50 0 10 25 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 10 40 10 13 14 14 0 13 40 13 38 52 75 53 0 10 25 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 10 50 10 15 15 15 0 15 50 15 50 60 90 60 0 10 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 15 55 15 20 20 20 0 15 55 20 50 65 100 70 0 10 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 11 11 12 12 10 10 11
Read Command Hold Time referenced to RAS tRRH
CAS Active Delay Time from RAS Precharge tRPC RAS to CAS Set-up Time (CAS before RAS) tCSR RAS to CAS Hold Time (CAS before RAS) tCHR
7/17
Semiconductor Notes:
MSM514256C/CL
1. A start-up delay of 100 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. VIH = 3.0 V and VIL = 0.0 V are reference levels for measuring input timing signals (speed ranks 45 and 50). 5. VIH = 2.4 V and VIL = 0.8 V are reference levels for measuring input timing signals (speed ranks 60 and 70). 6. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 7. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 8. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 9. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 10. tRCH or tRRH must be satisfied for a read cycle. 11. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 12. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle.
8/17
E2G0092-17-41E Semiconductor MSM514256C/CL
,,, , ,,,,
TIMING WAVEFORM
Read Cycle
tRC tRAS tRP RAS VIH - VIL - tAR tCRP tCRP tCSH tRCD VIH - CAS VIL - VIH - VIL - VIH - VIL - VIH - VIL - VOH - tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address Row Column tRCS tRRH tRCH WE OE tAA tROH tOEA tRAC tCAC tOEZ tOFF DQ VOL - Open tCLZ Valid Data-out "H" or "L"
Write Cycle (Early Write)
tRC
tRAS
tRP
RAS
VIH - VIL - VIH - VIL -
tAR
tCRP
tCRP
tCSH
tRCD
tRSH
CAS
tRAD tRAH
tCAS
tASR
tASC
tCAH
tRAL
Address
VIH - VIL - VIH -
Row
Column
tWCS
tWCH tWP
tCWL
WE
VIL - VIH -
tWCR
tRWL
OE
VIL - VIH -
tDS
tDHR
tDH
DQ
VIL -
Valid Data-in
Open
"H" or "L"
9/17
,,,
Semiconductor MSM514256C/CL Read Modify Write Cycle
tRWC tRAS tRP RAS VIH - VIL - tAR tCSH tCRP tCRP tRCD tRSH VIH - CAS VIL - tCAS tASR tRAH tASC tCAH VIH - Address VIL - WE OE VIH - VIL - VIH - VIL - VI/OH- Row Column tRAD tRWD tCWD tAA tAWD tCWL tRWL tWP tRCS tOEA tOED tOEH tCAC tRAC tOEZ tDS tDH DQ VI/OL- tCLZ Valid Data-out Valid Data-in "H" or "L"
10/17
, ,, , , ,,
Semiconductor MSM514256C/CL Fast Page Mode Read Cycle
tRASP tRP VIH - RAS V - IL VIH - CAS VIL - VIH - VIL - VIH - VIL - tAR tRHCP tCRP tRCD tPC tRSH tCRP tCP tCP tRAD tCAS tCAS tCAS tASR tRAH tASC tCSH tCAH tASC tCAH tASC tRAL tCAH Address Row Column Column Column tRCS tRCH tRCS tAA tRCH tRCS tAA tRCH WE tAA tRRH VIH - OE VIL - VOH - VOL - tOEA tCPA tCPA tOEA tOEA tCAC tOFF tCAC tOFF tCAC tOFF tRAC tOEZ tCLZ tOEZ tCLZ tOEZ DQ tCLZ
Valid Data-out Valid Data-out Valid Data-out
"H" or "L"
Fast Page Mode Write Cycle (Early Write)
tRASP tPC
tRP
VIH - RAS V - IL VIH - CAS VIL - VIH - VIL -
tAR
tRHCP
tCRP
tRCD
tRSH
tCRP
tCAS
tCP
tCP
tCAS
tCAS
tASR
tRAH tASC tRAD
tCSH tCAH
tASC
tCAH
tASC
tCAH
tRAL
Address
Row
tWCS
WE
VIH - VIL -
Column tCWL tWCH tWP tWCR tDH
Column tCWL tWCS tWCH tWP
Column tRWL tCWL tWCS tWCH tWP tDS tDH
tDS
tDS
tDH
VIH - DQ VIL -
Valid Data-in
Valid Data-in
Valid Data-in
tDHR
Note: OE = "H" or "L"
"H" or "L"
11/17
Semiconductor
Fast Page Mode Read Modify Write Cycle
VIH - RAS VIL - tAR
VIH - CAS VIL -
Address
VIH - VIL -
V WE IH - VIL -
VIH - OE V - IL VI/OH- VI/OL -
DQ
RAS-Only Refresh Cycle
RAS
VIH - VIL -
CAS
VIH - VIL -
Address
VIH - VIL -
DQ
VOH - VOL -
,,,, , , ,
tRASP tRP tCSH tPRWC tRCD tCAS tCP tCAS tCP tRSH tCAS tCRP tRAD tRAH tCAH tASC tASC tASR tASC tCAH tCAH tRAL Row Column tRWD Column Column tRCS tCWD tCWL tRCS tCPWD tCWD tAWD tCWL tRCS tCPWD tCWD tAWD tRWL tCWL tAWD tRAC tDS tWP tDH tDS tWP tDH tROH tDS tWP tDH tAA tCPA tAA tCPA tAA tOEA tOEA tOEA tOED tOED tOED tCAC tOEZ tCAC tOEZ
In
MSM514256C/CL
tCAC
tOEZ
Out
In
Out
Out
In
tCLZ
tCLZ
tCLZ
"H" or "L"
tRC
tRAS
tRP
tCRP
tRPC
tASR
tRAH
Row
tOFF
Open
Note: WE, OE = "H" or "L"
"H" or "L"
12/17
Semiconductor
,, ,,,
MSM514256C/CL CAS before RAS Refresh Cycle
tRC tRP tRAS tRP RAS VIH - VIL - tRPC tRPC tCP tCSR tCHR CAS VIH - VIL - VOH - VOL - tOFF DQ Open Note: WE, OE, Address = "H" or "L" "H" or "L"
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRP
tRAS
tRP
RAS
VIH -
tAR
VIL - VIH - VIL -
tCRP
tRCD
tRSH
tCHR
CAS
tASR
tRAD tASC tRAH
tCAH
Address
VIH - VIL -
Row
Column
tRCS
tRAL
tRRH
VIH - WE V IL - VIH - OE V IL -
tAA
tROH
tOEA
tRAC DQ VOH - VOL -
tCAC tCLZ Valid Data-out
tOFF tOEZ
"H" or "L"
13/17
,,, ,
Semiconductor MSM514256C/CL Hidden Refresh Write Cycle
tRC tRC tRAS tRP tRAS tRP RAS VIH - VIL - VIH - tAR tCRP tRCD tRSH tCHR CAS VIL - tASR tRAD tASC tRAH tCAH t RAL Address VIH - VIL - Row Column tWCS tWCH VIH - WE V - IL VIH - OE V IL - VIH - VIL - tWP tWCR tDS tDH DQ Valid Data-in tDHR "H" or "L"
14/17
Semiconductor
MSM514256C/CL
PACKAGE DIMENSIONS
(Unit : mm)
DIP20-P-300-2.54-W1
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP.
15/17
Semiconductor
MSM514256C/CL
(Unit : mm)
SOJ26/20-P-300-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
16/17
Semiconductor
MSM514256C/CL
(Unit : mm)
ZIP20-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP.
17/17

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